for those wondering, it sounds like from the interview, that zen 5 is 8 wide decode, but can only decode from one branch path of a single thread at a time per that decode unit. so real world gains would still be only around the previous zen 4 offerings of 4x ILP.
Going to 16 cores on a single ccx would reduce core to core latency, but they will probably need upgrade their ring interconnect to either a 4x4 tile interconnect or something better.
the reasoning behind using vega apu's instead of RDNA MAYBE because agreements with Microsoft and Sony who probably don't want AMD to release other rdna apu's potentially "piggybacking" off of funding they provided AMD to develop their console apu's
already posted this on Reddit but here is my opinion 'The internal, in-depth, story of Intel's mistake was that the designed their node for sustained high frequency performance where as TSMC designed their node to be you know be 'manufacture-able" '
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