Recent content by ricebunny2020

  1. R

    Discussion Apple Silicon SoC thread

    Rosetta does not support the translation of AVX, AVX2, and AVX512 instructions.
  2. R

    Discussion Apple Silicon SoC thread

    Has anyone else noticed how the same Tiger Lake chip performed 20% slower in SPEC 2017 in the M1 review compared to the review they did 2 months ago? It would help a lot if Anandtech documented what compilers and settings they used to build the SPEC 2017 benchmarks they used.
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