Recent content by MS_AT

Let's also keep in mind that performance of CB24 scales much more with memory subsystem than CB23. https://chipsandcheese.com/p/cinebench-2024-reviewing-the-benchmark The memBW available to single CCD on Strix Halo is 1/4 of the total memory BW. 1/2 of total memory BW for MT loads. There is also...

Advocates of dual x3D chips might not like the conclusions. On the other hand, I wonder how the author has handled the internal game settings for SMT. As the game by default, in theory, should use 1 worker per core for 2CCD chips. It should be now possible to modify that in the options, but I...

https://videocardz.com/newz/amd-ryzen-9000-cpu-with-16-zen5-192mb-of-l3-cache-and-200w-reportedly-on-the-way some people will be happy if this turns out to be true;)

According to this https://chipsandcheese.com/p/running-spec-cpu2017-at-chips-and-cheese?utm_campaign=post&utm_medium=web they are using -mcpu flag, which is deprecated version of -mtune, which in theory tunes the code for the native architecture but does not enable instruction set extensions...

And now we will get people saying if 285K gets higher IPC than Zen5 in games, it was unjustly bashed for its gaming performance;) You could have at least added the systems specs for both tests. So the Intel system was running memory at DDR5-6000 28-36-36-96, and had E cores disabled in the BIOS...

https://chipsandcheese.com/p/running-gaming-workloads-through a pity he doesn't have a x3d part to compare.

Obviously my math was wrong;P From throughput/c alone, 32E cores should be equal to 16 Zen6 cores. I must have assumed 8 P cores for some reason. Know this message as well as previous message is only about throughput per cycle. It says nothing about real performance. Just to make it clear...

That is problematic, I don't know what power the CPUs consumed in his tests, he did not put it on the sldies. Then I don't know how to account for various platform differences that also influence the outcome. There is also memory BW and latency difference to account M4 will have much better BW...

You mean this one?;)

Yes, we are better of forcing CPU affinity to avoid E cores on Meteor Lake, sticking to P cores + HT. On HX RaptorLake with 8P cores and 12 E-cores usinig E-cores gives us tiny benefit. Needles to say people look at Strix Halo with longing, but probably Arrow Lake would do. This is at work, data...

Seems relevant, but keep in mind they admit AMD is sponsoring the piece in some way https://www.servethehome.com/deploying-amd-instead-of-arm-in-our-infrastructure-2025-here-is-why/.

If you mean to disable interrupts around problematic code to ensure the kernel will not tick and try to reschedule when you are executing problematic code, then good luck to you;) How would you decide the granularity of critical section? After every instruction? After every 10 instructions? I...

Well, HT/SMT exists to find ways to ensure backend resources are not idling. If somebody writes code with full backend utilisation in mind and knows what he/she is doing, then of course HT won't provide the benefit for this task, but code tuned to this degree is rarely encountered in the wild...

Do you expect the OS to inspect instruction streams of the apps and to be able to do some sort of disassembly to be able to understand a forbidden instruction is going to run?;) Remember that OS ticks are milliseconds apart. It would need to inspect the code thousands of cycles ahead and then...

It's kind of funny that people mix ARM with Apple. It's Apple that is both ahead and have usable ecosystem. I mean the Snapdragon 8 Elite is waste as mobile SOC, aside from throttling android is not a platform that would allow you to easily use the chip for productive tasks. Android should...