Recent content by Mortius

The answer is power and can be found in this June 2014 WCCF post (it seems this time they had accurate information). Look at the power requirements of DT 4+4e compared to 4+2. 4+4e: VccGT requires 4 phases and a GTUS rail 4+2: VccGT requires 2 phases and no GTUS rail. For a measure of...

Qualcomm without its chip business is nothing but a 114 billion dollar patent troll with no need to cross license. Compared to them, Apple and Microsoft would look like innocent boy scouts.

One further point The use of the word "promise" suggests that you do not know what Intel actually said. Any announcement that they make regarding future plans is almost certainly accompanied by a statement that looks something like this: With a disclaimer of that length, which points to one...

I suppose you are still upset that we don't have 10GHz CPUs by now. Apparently that was considered a very disappointing prediction as it was supposed to have been 128GHz processors instead.

Did you actually read this article? I'm surprised you didn't pick up on what is highly damning evidence of Intel's delays. The first paragraph of the article: Current die sizes are >100mm^2, yet apparently Intel will start making dies with a size of 10nm (presumably on one side only). The...

For the post acquisition history of OCZ, there is also Anandtech's rather flattering interview with them. A pity it isn't always clear which of the content is from the interviewer and which is from the interviewee.

Ah yes. Their first Indilinx based drive was a record breaker. 52.07% return rate, and a clean sweep of the board for return rates above 5%. (French, but easily understandable)

Going by the same scaling metrics, Sofia 3G would work out at ~25mm^2. (Exactly four of its dies fit into the bay trail one, give or take a bit of rounding) Given that it is being fabricated on a 28nm process and won't have significant density improvements, is this reasonable?

It seemed to work for Amazon.

Your credulity is rather lacking. The secret to Broxton is taking Bay-Trail and scaling it down so that all of its components exist, but are proportionally smaller. To adapt it to a mid-range smartphone with inbuilt 4G is achieved by making everying proportionately smaller yet again. Swap out...

TSMC badged slide stating that 16nm is 10% denser than 20nm I suspect that part of the problem may be because of TSMC's decision to have two "16nm" nodes. Intel's slide shows a comparison against 16FF with its marginal improvement. TSMC's slide is using their 16FF+ process which improves the...

Intel R&D Expenses Lets assume that it takes two years to develop both the process and the cpu. Expenses in the lead up to Haswell: 20.169 Billion USD Expenses in the lead up to Penryn Quads: 11.628 Billion USD Research and Development expenses have approximately doubled, (assuming they...

You are assuming that either a) Production cost is the sole cost involved in releasing a CPU. (Good news. Sales and marketing, customer support and actually designing the thing is free) or b) Every other cost scales in proportion to design cost. Lets assume that for the Q8300 100 engineers...

That device's purpose is to act as a fuse for the USB ports at F_USB1. It is meant to burn out to protect the rest of the motherboard (or anything connected via USB for that matter). I would say it is unlikely that the fuse killed the power supply, but it is plausible that a dying power supply...