Recent content by mat9v

Ok, I bow to your guys superior knowledge of how console processors are built :)

They are, 4 2-core complexes (grouped by 2) all connected by L2 cache - long comparison to CCX connected by Infinity Fabric even if "communication between them is not ideal". But ok, you have a point there that it resembles CCX in Ryzen :)

No, consoles do not have CCX, they are based on Jaguar core, if anything they have 2-core complexes, four of them. You are right, you were testing worst case scenario :) Now I have to see that for myself on my PC :) so just have to find some time to do the tests.

What does console design have to do with it? Console CPUs do not have CCXs. I was talking about forcing games to run on 4 cores belonging to one CCX or 2+2 from different CCXs in Windows by pinning them to cores - you can test any configuration that way - it's just that you can't simulate real 4...

So it seems. I will test it myself in various games in 2+2 and 4+0 config then in Windows with forced cores association with 8 cores active.

So it seems my error was in not completely powering down my PC between changes. How stupid of me...

I have no idea what you are implying - 4+0 (8MB of L3) as in Ryzen 1200/1300X/1400 is in fact 2+2, it is not 4+0. They are Ryzen cores that have errors in "lower" or "upper" halve of L3 cache (look at CCX schematics how that works). And yes, differences in games are there but due to cache size...

Nope, even on R7 you can't get 4+0 config. I know, I have tried on few boards. You only get 2+2 even if you select 4+0. Ping core to core shows that it is not working. Yes, I can use more then 4 threads, but not cores. Windows prefers cores to threads and it won't put a 5th thread on SMT core...

There is no way to test such because bios setting between 2+2 and 4+0 are ignored. You could conceivably test it by forcing program to use specific cores but that would require R7 CPU to even try and the results would be tainted. You can't test 2+2 / 4+0 on 1500X anyway - bad example.

And increased L2 cache sizes - in all, small decrease. You ask, why would I be left with cross-CCX traffic - because some programs (games) use more cores and while Windows is aware of CCX topology, when the game requests 6 threads and they can't be on 4 cores because of load balancing, it...

1. Cores inside CCX are not connected to each other, they are only connected to L3 cache - so only 2 additional links to L3 cache would be needed. https://www.custompcreview.com/wp-content/uploads/2017/06/amd-ccx-epyc-cpu-presentation-slides-1.jpg - there you can see 6 links inside L3 cache and...

Unless the CCX would grow to 6 cores, as I suppose it is "destined to" grow in 7nm ;) While 3 CCX complexes would complicate things, two bigger ones would largely not affect the overall design - after all CCXs are connected to IF by L3 cache and you would simply add cores and connect them to L3...

Well, they might have been able to do it like this: i.redditmedia.com/--EzP2t4YMf9TCYeibbG29tu3Ajfeje5QjrvCk8g1uI.png?w=572&s=d4d21987be37de7cfc9679f1aff4d5ea - but I do not know if RyzenMaster would correctly show it as 4500Mhz.

I was just curious about your opinion, if their results came from specific configuration of 2700X CPU and if so why did 1800X also cross power limit - if it was a standard case for those Ryzen CPUs. I have found an interesting review -...

According to above numbers, 1700X or 1800X also did not respect power limits - is that what you have noticed in your tests too?