Recent content by Manabu

But if wasn't for those upgrades it it wouldn't have lasted 10 years, right? One thing to be observant off is what comes soldered in those new laptops, and thus not upgradable/repairable. Some, fortunately rare, come with storage soldered. Most are coming with RAM soldered, even Thinkpads. LPDDR...

I would bet in four CCX per chiplet, with 4 cores per CCX. Why? Because it would be reusable for lower end monolithic mobile cpus, like Mendocino and Steam Deck's APU that right now are stuck in Zen2 because Zen3 and Zen4 are 8-core CCX. 8 big cores is too much leakage for those power limited...

Sorry, I don't know what SLC means in this context. Single Level Cache? That is why I prefaced with reduction in FP compute power compared with the vanilla Zen4 core, speculated here. If that change is in the tables, then an L1 amount change might also be, as both means changing the floor plan...

Nobody is speculating on the quantity of L1 cache for Zen4c/D? It will be optimized for a lower peak clock speed and according to AMD will have a new cache hierarchy. I doubt that refers only L2 and L3 cache. If they will fiddle with removing FP compute power, they can also fiddle adding extra...

It seems I was wrong on betting on pasive interposers this time. From the photos, it seems the same MCM with IFOP between the dies. Points to kokhua. But nobody here guessed the actual disposition of the chiplets around the IO die. Now I believe Matisse might be indeed a single 7nm die. No, I...

It was basically a repetition of what he already said here. But I want to comment on one point I forgot: I don't see why stitching would be needed. You only need to print connections in the center part of the interposer, up to 2~3mm from each side of the borders of the SC die. Then the...

Zero warning points, but just got 76 trophy points in two days (60 yesterday, before making my first post).

Well, in my thoughts the "heatsink chiplet" would likely be of a more complex shape than the rectangles pictured, with holes in it for the other actual chiplets to fit in. If fitted first, it could even aid the correct positioning of the other chiplets. Well, for my non-HBM2 Matisse idea, it...

I really liked the idea of active interposers. It offers lower latency and thus higher performance than passive interposers, due to the shorter signal paths. Also, the possibilities with 3D layout of the function blocks (butter donuts and whatnot) are very exciting. The heat dissipation is...