Recent content by looncraz

I'm going all core and letting the clocks jump around... seems there's a good chunk of performance left on the table doing that...

Fixed!

5.97GHz, but some jumping around of the clock... pretty sure this is the limit of this CPU... since I won't apply extra voltage (in fact, this is -12 curve optimizer and 125MHz PBO boost... and nothing at all else... -15CO fails to boot, but does POST, so we're at the limit)

Ryzen 9 7950X bone stock, but using a custom loop. Running through WINE, though it doesn't appear to impact the score at all... Frequency was 5.88Ghz during most of the test - ran it three times, very little variation.

I did a test with a 5950X at 5GHz and scored 903... within 1.2% of the same 5.6Mhz/CPUMark99, so close enough to say you seem to be right. Is CPUMark99 x87 heavy?

5950X @ 4Ghz: @ Stock: @ best core, locked affinity (4.9~5.0GHz) All run under Linux, 5.5.2, so there's some minor WINE overhead, however that doesn't seem to impact the score at all. Update: 5950X 5Ghz

Ryzen 5 3600X, stock, 4.4GHz (maybe...). Xubuntu 19.04, custom systemd, wine64 764 Will try again in Windows... EDIT: 765 EDIT: Running AGESA 1003 ABBA EDIT: Running AGESA 1004B, Ryzen 9 3900X, 4.525GHz (stock!)

Not the first time I'd be the first to discover an AMD bug :p Now I just need to find someone who wants to buy Thread Ripper... I have two or more buyers for a good Zen-based APU (those are always easy sales thanks to HTPCs). My retirement is going well... LOL!

Literally the first thing I checked after updating to 1006 a couple weeks ago. Still a no go, ntvdm 100%, nothing runs. However, that's better than it was. Before, ntvdm would only randomly launch, then it would just never launch again. Now I can have multiple ntvdm processes running maxing...

The behavior is exactly as expected for a bifurcated victim cache (or dual independent victim caches). The Ryzen 5 1400 has 8MB of L3 total, in two 4MB chunks. Allocating 4MB will not entirely end up in the L3 - some will be in the L2, some will be in the L3, and some will not be on-die at...

Only two P-states are available to software P-State 1 and P-State 2. P-State 0 is a hardware-mediated turbo that won't be engaged (but will determine the TSC frequency) and 'higher' P-states are for low power modes.

This is when kernel thread leveling acts to improve performance by forcing both L3s to have the data. If a CCX is parked, it will never have the data.

Cache aware algorithms expecting access to 16MB of L3 cache and allocating pools that are larger than 8MB.

Nothing wrong with that when the power draw is as low as with Ryzen. I don't see many boards at all having difficulty handling 1.4V 8-core at 4Ghz.

Swapped the Prime X370 Pro with an ASRock Fatalwhatever Gaming K4. Generally better options, though not all fan headers can run in DC mode... only real downside I could find. Did not resolve virtualization issue, so I will assume that we will just have to wait for the software ecosystem to...