CouncilorIrissa's latest activity
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CCouncilorIrissa reacted to Doug S's post in the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads with
Like.
I think those myths arise because some want to deny Apple credit for its accomplishments. So Apple's CPUs are only able to do what they... -
CThere are no "virtual" cores. There are no "real" cores. There are just cores and some of them happen to be able to support two hardware...
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CCouncilorIrissa replied to the thread Question Zen 6 Speculation Thread.Doesn't change anything for the sibling threads. edit: 1.2.0.2b AGESA result:
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CCouncilorIrissa replied to the thread Question Zen 6 Speculation Thread.I'd also add there's little gain in thread-to-thread latency between sibling threads on the same core rather than threads on different...
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.At the end of the day, even with 1/4 of a L2 slice the core is anything but huge, which seems to be the myth perpetuated by many when it...
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.The L0 cache isn't "new", it's just a marketing gimmick. It really is just a renamed L1. Same capacity, similar bandwidth, standard 4...
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.So what you're saying is that we should arbitrarily discard certain parts of the core from the calculation because Intel needs three...
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.Following your logic we would need to add Intel's L3 to the core area then, because it's also a shared cache.
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.Why would I exclude L2? It's a core-private cache.
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.That's what I said about core-private caches? Apple's P-cores core-private cache is L1 and is included in the area, L2 excluded. For LNC...
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CCouncilorIrissa replied to the thread Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads.No? Accouting for core-private caches only, M4's P-core is at ~3mm^2 and LNC is at 4.6mm^2. I don't know where this myth of enormous...
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CCouncilorIrissa reacted to StefanR5R's post in the thread Question Zen 6 Speculation Thread with Like.
… with AMD: the PPT limit, … with Intel: PL2 and how long it is allowed to be sustained (possibly indefinitely, if set so in the BIOS)...
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CCouncilorIrissa reacted to Doug S's post in the thread Discussion Apple Silicon SoC thread with Like.
I don't think that matters. Most software doesn't have an "x86" and "arm" branch, it has a Windows branch, a Linux branch, and a macOS...
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CCouncilorIrissa reacted to StefanR5R's post in the thread Question Zen 6 Speculation Thread with Like.
(more cores for better interactivity?) Let's say you have two cores in your system. One is busy for 3 % of its time, the other is...
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CCouncilorIrissa reacted to adroc_thurston's post in the thread Question Zen 6 Speculation Thread with Haha.
They've already validated SMT for classic. I have a bridge to sell to you If you think this is a relevant metric anyone cares about.
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