Recent content by coercitiv

and comes with a longer warranty

You also need to take into account the pressure on the L2 cache, when running heavy MT loads the E core has to work with less effective L2. That's one of the perks of the P core, their own L2 cache with a beautiful private alley to ringbus valley.

AMD copies Nvidia twice, so they get double the performance. AMD fools, they could have copied thrice.

I refrained from posting this morning after reading the news, because it felt like I lacked the proper description for what is happening. Your choice is perfect.

Not sure what you mean by that, I'm not arguing they should follow the same path as AMD. I'm saying their previous choices favor certain decisions, some because they lean on their strengths and others because they fix weaknesses. My personal expectation was to see Intel revert to MC on the...

Not when discussing yields and flexibility. If they pay the performance price for off-die mem controller, then might as well use multiple smaller tiles for better yields & better binning. Think of a P-tile and E-tile for example, both ~60mm2 each. They could generate their entire lineup with...

Counter examples for what? Why? Poster 1: AMD showed they're catching up in RT. Poster 2: I have no idea where you see AMD is better than Nvidia at all, they just come up with cloned tech years later. Poster 3: I see you're very susceptible to marketing. The response to Poster 1 is just a way...

I'll go quickly through your questions: Is NL going to really double the core counts - Very unlikely to happen to their whole lineup, possible to happen for one/few ultra premium SKUs (ultra pun intended). Some of this core count increase may trickle down to value SKUs, but only a fraction. Is...

Asus Silent Stutter Edition Don't you guys like to have options?!

To me this looks less about tick-tock and more about which IP they have available for a given node. They even tried to give it a new name. MTL is a tock and a shrink - the change to tiles is huge. LNL completely re-imagines the internal structure of an Intel mobile CPU, even if the core...

There's also a distinct possibility that his reign was doomed from the start, no matter the person in charge. Intel's top and middle people would resist and sabotage the required changes until the company was in ruin. (I suspect even their board was in denial) One analogy comes to mind, and...

I intentionally left that out of the post as it was getting bloated already. Even if we somehow solve the CPU bottleneck, there's still the issue with diminishing returns in terms of perception: for a human being the jump from 5 seconds to 0.5 seconds has a bigger impact than the jump from 0.5s...

When it came to the speeds that powered systems responsiveness (mostly random 4k read/write) the gains you had with first gen of SSDs were over an order of magnitude. We went from random operation performance like 0.5 Read (MB/s) and 1.5 Write (MB/s) to something like 15-20 Read and 20-60 Write...

Yes, and Lip-Bu Tan is the fourth CEO in four years :)

"I talked about this in the past" in the sense that I already mentioned this issue of theirs, not that they've stopped doing it.