Recent content by BorisTheBlade82

Idk. This would need a very deep understanding by the Scheduler of what a thread actually does - at runtime. IMHO nowadays, Schedulers more or less only regard the applied priorities and some Monitoring Data like current Processing demand. I personally think that every form of categorization...

Sorry, but I need to disagree. If that worked like a charm as you say, how come that Intel fused off AVX512 from Alder Lake onwards in order to present Compilers and OS a homogeneous ISA? Even if Compilers were able to handle this, everything would have to be recompiled, which in itself is a far...

@Z O X & @LightningZ71 Great to at least see two people here thinking of R.E.M first as well when seeing this line - Kudos 😄

Basically, it is the interconnect and everything belonging to it, as has been said already since the ineption of Zen 2.

Fair point 👍🏽

Weren't the Last Gen SoCs basically Zen2 CCD with a heavy iGPU slapped on, that competed for the same TSMC 7nm capacity as their Desktop and Server derivatives at that time? What reason do we have to expect, that their next incarnation should be much further away from their PC Bleeding Edge...

Apart from this not really being disputed just because of German(-ish) being spoken in some valleys around there, there is another Verano next to Piacenza 😉 https://maps.app.goo.gl/NpXM9gDRvrdDgNrKA

Then you are pretty much alone with your line of thinking. Every piece of information and every half credible leak points to 32c for Venice Dense and 12c for Venice and Desktop.

There is also a Verano next to Bozen. https://maps.app.goo.gl/Tckpm7dWRTN599ua7

Yep, that interests me as well. And they do not double, they almost triple. 1.6 TByte/s / 576 Gbyte/s = 2.77

To keep per core RAM BW constant, they would need a 128 GByte/s D2D interface BW compared to 64 GByte/s GMI narrow. To keep RAM BW : CCD BW of roughly 10:1 constant, they would need around 170 GByte/s. That should obviously be the range for Desktop Venice too, finally allowing it to use all the...

Must be, as 256/12 (c Venice CCD) would be 21.3 CCD 🤷🏽‍♂️

@Everyone I meant RAM BW, not TDP. Sorry - thought that was obvious.

That's around 3x of EPYC Turin, isn't it? What kind of RAM and how many Channels will they be using?

@adroc_thurston is on record for stating that they have a separate CCD. I still find this a bit unbelievable for such a small volume part, but we will see.