Recent content by bakyt115

is it true that zens loose predecoding(instructions boundaries mark) L1i ?

what the reason of this? without smt it is as good as 2P

what means different IPC data? dedicated for int and fp?

flashed HX 375 scores on LNL review

cb 23 multy

what about GPD claims? they are still exists in their web site. https://gpd.hk/gpdduo

there was paper about power consumption of x86 (in comparison with arm). and there was statement that decoding consume nearly 20% (can be wrong in numbers can't find article itself) of power for old tiny atom cores. may be second decoder is now issue for zen5 core to hold max frequency in 1t...

to save area

as I understand from tremont discussion second decoder should decode second path of branch

may be if someone with 370 in hand can disable SMT and e cores and makes some test then we can compare results with 4 core zen4 also interesting to see core to core comparison with SMT on and off.

also AMD didn't provide any data how much improvements gives second decoder for NT.

seems like second decoder is not used in 1T.

which of zen5 products will be on 3nm?

what means "on the move" on battery?

choooo chooooo! hype train alive again!!! mooooore mooooore fuel it is still not enough this forum will be hot like a hell until final test I think after final tests we will still hear voices like node broken, bios broken .....