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Io Magnesso
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Jun 12, 2025
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Io Magnesso
replied to the thread
Discussion
Apple Silicon SoC thread
.
Well, no matter how much Apple silicone or high-performance MAX, it can't be helped if throttling occurs due to the setting. What...
Yesterday at 10:34 PM
Io Magnesso
reacted to
poke01's post
in the thread
Discussion
Apple Silicon SoC thread
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Interesting, anyone else notice the same? Going from A17 Pro to A18 Pro? Or M3 to M4? More confirmation that N3B was a troubled node
Yesterday at 10:32 PM
Io Magnesso
replied to the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
.
As expected, I understand that there are people who want to complain that there are only 2 cores of P cores. As expected, it's not as...
Yesterday at 10:29 PM
Io Magnesso
reacted to
DavidC1's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
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Like
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Gracemont Quad was only about 15% larger than a P core, and Uncore portion takes up quite a bit. Skymont quad is still not enormously...
Yesterday at 10:24 PM
Io Magnesso
reacted to
poke01's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
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Like
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I actually think Nova Lake will be bigger than alder lake and arrow lake. It’s one of those architectures where you will instantly...
Yesterday at 10:24 PM
Io Magnesso
reacted to
dullard's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
with
Like
.
That has been Intel's plan all along. The image below was 5 years ago. More NPU for corporate employees, more graphics for gamers...
Yesterday at 10:23 PM
Io Magnesso
reacted to
dullard's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
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Like
.
It absolutely is unlikely to be the ideal core count. If I were Intel, I would design a 48 core E-only tile that is just about the same...
Yesterday at 10:23 PM
Io Magnesso
reacted to
511's post
in the thread
Question
Intel's future after Pat Gelsinger
with
Like
.
they already are lol the C variants that were supposed to cost optimized version are now more expensive by double digit lol there goes...
Yesterday at 1:28 PM
Io Magnesso
reacted to
DrMrLordX's post
in the thread
Question
Intel's future after Pat Gelsinger
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Like
.
Wafer prices are going to be awful if they're the only ones left at the top.
Yesterday at 1:28 PM
Io Magnesso
reacted to
511's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
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Like
.
well it's not tbh 8+16 is going to be the Ultra 5 and yeah the U5 is going to kick U9 285K in the back so hard it would be hilarious and...
Yesterday at 1:28 PM
Io Magnesso
reacted to
511's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
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Like
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Yeah but in the end it's up to Intel to get their priorities right they just need to have 15-20% better gaming performance than X5 X3D...
Yesterday at 12:44 PM
Io Magnesso
reacted to
gdansk's post
in the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
with
Like
.
We should be able to fit at least 80 'monts in a dual tile setup. Give the throughput people maximum throughput, Intel.
Yesterday at 12:44 PM
Io Magnesso
replied to the thread
Discussion
Intel Nova Lake in H2-2026: Discussion Threads
.
It may be possible if the core per one is made incredibly small...
Yesterday at 12:44 PM
Io Magnesso
reacted to
LightningZ71's post
in the thread
Question
Zen 6 Speculation Thread
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Keep in mind, for AMD, they treat designs like building blocks. The current rumor mill has AMD preparing two mass market chips relevant...
Yesterday at 12:08 PM
Io Magnesso
reacted to
Kepler_L2's post
in the thread
Question
Zen 6 Speculation Thread
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Zen6 and Zen6c both exist in N3P and N2P.
Yesterday at 12:07 PM
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