I quote below what the documentation says, nothing about any errata, and all seems to reinforce my original point, by disabling Halt Detect the Motherboard BIOSīs are wasting power, and not allowing the self cooling capacity the processor has built-in.
Some valid reason should however exists to disable it because all mobo manufacturers are doing the same, if this is a highly technical forum I thought was one posible place to find the answer .......
Document #237921- June 2001 AMD Athlon Processor Model 4 Data Sheet
Chapter 4 page 9:
The AMD Athlon Processor Model 4 supports low-power Halt
and Stop Grant states. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating
systems for processor power management.
When the AMD Athlon Processor Model 4 executes the HLT
instruction, the processor issues a Halt special cycle to the
system bus. The phase-lock loop (PLL) continues to run,
enabling the processor to monitor bus activity and provide a
quick resume from the Halt state. The processor enters a lower
power state if the system logic (Northbridge) disconnects the
AMD Athlon system bus in response to the Halt special cycle.
Stop Grant States
The AMD Athlon Processor Model 4 enters the Stop Grant state
upon recognition of assertion of STPCLK# input. There are two
mechanisms for asserting STPCLK# - hardware and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This task is accomplished by asserting the
THERM# input to the Southbridge. Throttling asserts
STPCLK# for a percentage of a predefined throttling period:
STPCLK# is repetitively asserted and deasserted until the
THERM# pin is deasserted.
After recognizing the assertion of STPCLK#, the AMD Athlon
Processor Model 4 completes all pending and in-progress bus
cycles and acknowledges the STPCLK# assertion by issuing a
Stop Grant special bus cycle to the AMD Athlon system bus.
After the Northbridge disconnects the AMD Athlon system bus
in response to the Stop Grant special bus cycle, the processor
enters a low-power state dictated by the CLK_Ctl register.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, and SMI#, or local APIC interrupt message igf they
Connect and Disconnect Protocol
Significant power savings of the AMD Athlon processor model 4
only occurs if the processor is disconnected from the system bus
by the Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant
special cycle. Reconnect is initiated by the processor in
response to an interrupt for Halt, STPCLK# deassertion, or by
the Northbridge to service a probe
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles