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Old 12-26-2001, 07:22 AM   #1
gustavo
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Default HALT Command Detect (Why disabled by default ?)

I own an MSI K7T266 PRO, Windows 2000 Professional SP2 and a TBird C series 1GHz.
I downloaded a program named WPCREDIT and documentation regarding PCI Configuration
Registers for the KT266/KT266A chipset from http://www.viahardware.com/download/viatweak.shtm

Specifically I point to the information about the register 95. Setting it from the default
of 1C to 1E my cpu temperature at idle went down from 49C to 33C. Incredible output !!!

The documentation of the plugin to use with wpcredit and KT266/KT266a unveils that the STPGNT
Detect is located at Register 92 and enabled by default in the MSI 6380. What is not enabled
is HALT Command Detect, located at the Register 95. Setting the Register 95 to 1E enables
HALT Command Detect.

16C down is very attractive and many users I have contacted are obtaining the same results.
Using other mobos (not MSI) they have to enable STPGNT Detect besides HALT Detect, the MSI has
it allready enabled.

So my questions are:
Is there any official information regarding this ?
Is there any reason why is 1E not set by default at Register 95 ?
Are there any side-effects of setting Register 95 to 1E (ie hardware damages, data corrruption) ?
Any idea will be very appreciated.


Gustavo.-:frown:
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Old 12-26-2001, 10:36 AM   #2
AndyHui
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STOPGRANT is needed for SMP as well as halting the processor.....IIRC...but I'm not sure about that.

I do know that HLT is disabled for the ASUS A7V266 and possibly the A7V266-E (again, not sure about this one, since I haven't had a chance to check). This was implemented in a recent BIOS update. I can't remember the reason, but I will go see if I can find it.
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Old 12-26-2001, 01:00 PM   #3
gustavo
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AndyHui: Many thanks, will keep around looking forward for your findings.

One theory I heard, but just pure theory without any documentation to base it on is that disabling this function you reduce the transient current on the cpu in a way that the cpu always stays in a state where the minimum power consumption stay at least half the peak current (or about). Since the HLT put the cpu in a sleep state, the current draw under this state in very low. And because the HLT is issued and deissued at high frequency to sleep the cpu between process load in windows it generates a sort of irregular current pulse of large amplitude, going from 3 to 20 to 3 amp . Good voltage regulators can cope with this but it put some extra burden. Which in turn allows MB manuf. to put the crappiest voltage regulators without having too much RMA.

Sounds reasonable to you ?
Any idea from somebody else ?


Thanks Gustavo.-

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Old 12-26-2001, 07:28 PM   #4
Peter
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The T-Bird core has two errata that imply that Halt detection (to be more exact, Disconnect-on-Halt) shouldn't be enabled.

If these have been fixed in Palomino/Morgan, then it should be OK to enable. It's about power saving when idle. Nothing to do with SMP.

edit: ... and gustavo is right, the transition from and to power-saving Halt mode is the hardest test for the CPU voltage regulators. Actually, voltage regulator compliance testing is done by running a worst-case power consumption software while periodically HALTing the processor while watching by how far the voltage moves. However, you can't cheat much here since you can get around the HLT instruction initiated Disconnect, but not the chipset initiated hard suspend request. Disabling Suspend altogether was very popular with some early Pentium mainboards that tried to become "compatible" with the early, power hungry Cyrix chips without reinforcing the voltage regulators.

regards, Peter
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Old 12-27-2001, 04:03 AM   #5
gustavo
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Peter:

What would happen (considering the two errata you mentioned) if Halt detection were enabled on a TBird ? Mine is a TBird C sries (is this a Palomino?) and the only thing I notice is that is running about 15C cooler at idle having enabled HLT detect using Wpcrset.

I mean what could I look for to feel I am on the safe side ? Should I leave HLT disabled ? (I am scared of breaking something). Should I expect a voltage regulator failure at the cpu level ?

It seems that all BIOS for Socket A boards have disabled the bit that determines HLT detect and some have also disabled the STPGNT detect.

Many thanks Gustavo.-
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Old 12-27-2001, 04:43 AM   #6
Peter
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see for yourself - the document (Athlon model 4 revision guide) is on AMD's web site. No hardware failure to be expected, the issues are functional ones.

regards, Peter
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Old 12-27-2001, 08:00 AM   #7
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I quote below what the documentation says, nothing about any errata, and all seems to reinforce my original point, by disabling Halt Detect the Motherboard BIOSīs are wasting power, and not allowing the self cooling capacity the processor has built-in.

Some valid reason should however exists to disable it because all mobo manufacturers are doing the same, if this is a highly technical forum I thought was one posible place to find the answer .......

Regards Gustavo.-

Document #237921- June 2001 AMD Athlon Processor Model 4 Data Sheet
Chapter 4 page 9:

The AMD Athlon Processor Model 4 supports low-power Halt
and Stop Grant states. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating
systems for processor power management.

Halt State
When the AMD Athlon Processor Model 4 executes the HLT
instruction, the processor issues a Halt special cycle to the
system bus. The phase-lock loop (PLL) continues to run,
enabling the processor to monitor bus activity and provide a
quick resume from the Halt state. The processor enters a lower
power state if the system logic (Northbridge) disconnects the
AMD Athlon system bus in response to the Halt special cycle.

Stop Grant States
The AMD Athlon Processor Model 4 enters the Stop Grant state
upon recognition of assertion of STPCLK# input. There are two
mechanisms for asserting STPCLK# - hardware and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This task is accomplished by asserting the
THERM# input to the Southbridge. Throttling asserts
STPCLK# for a percentage of a predefined throttling period:
STPCLK# is repetitively asserted and deasserted until the
THERM# pin is deasserted.

After recognizing the assertion of STPCLK#, the AMD Athlon
Processor Model 4 completes all pending and in-progress bus
cycles and acknowledges the STPCLK# assertion by issuing a
Stop Grant special bus cycle to the AMD Athlon system bus.
After the Northbridge disconnects the AMD Athlon system bus
in response to the Stop Grant special bus cycle, the processor
enters a low-power state dictated by the CLK_Ctl register.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, and SMI#, or local APIC interrupt message igf they
are asserted.

Connect and Disconnect Protocol
Significant power savings of the AMD Athlon processor model 4
only occurs if the processor is disconnected from the system bus
by the Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.

AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant
special cycle. Reconnect is initiated by the processor in
response to an interrupt for Halt, STPCLK# deassertion, or by
the Northbridge to service a probe

The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles
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Old 12-27-2001, 09:57 AM   #8
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gustavo, that's from the Datasheet (the specification document describing how it SHOULD be). You want to read the Revision Guide (the real-life document about what doesn't work as described in the datasheet).

regards, Peter
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Old 12-27-2001, 12:57 PM   #9
gustavo
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Thanks Peter, I am learning with you.
The errata described there follow and none appears to justify disabling HLT detect:

5 - MCA Bus Unit Control Register MSR 408H Returns Incorrect Information
10- Resistance Value of the ZN an ZP Pins
11- PLL Overshoot on Wake-Up from Disconnect causes auto-compensation circuit to fail
13- Instruction Execution deadlock
14- Processors with half-frequency multipliers may hang upon wake-up from disconnect
15- Processor does not support reliable microcode patch mechanism
16- INVLPG instruction does not flush entire four-megabyte page properly with certain linear addresses


What leaves the original question still unanswered.
Gustavo.-
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Old 12-27-2001, 01:59 PM   #10
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<< gustavo, that's from the Datasheet (the specification document describing how it SHOULD be). You want to read the Revision Guide (the real-life document about what doesn't work as described in the datasheet).

regards, Peter
>>



I was under the impression that the datasheet for the bus disconnect erratum was not easily available (isn't that the one which gives the updated timings?)
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Old 12-28-2001, 08:26 AM   #11
gustavo
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CTho9305: The errata you refer follows....

11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail

Non-conformance: The AMD Athlon Processor Model 4 PLL can exceed the normal operating frequency when reconnecting to the system bus after a disconnect, causing a failure to maintain sufficient system bus I/O drive strength levels in the driver compensation circuit. The compensation circuit attempts to correct the drive strength, but if there is not sufficient time to perform this function, the system bus cannot operate properly.

Potential Effect on System: The system hangs.

Suggested Workaround: The event can be avoided through BIOS manipulation of the reconnect timing using the CLK_CTRL MSR. The time for the PLL to overshoot can be greatly shortened to reduce it to a very small time period that does not enable the failure, and the time between the rampup and the reconnect to the system bus can be increased such that a failure in the compensation circuit has enough time to recover before reconnecting to the bus


The suggested workaround does not seem to be disabling the HLT detect, or is it between the lines and I did not understand it ?

Thanks Gustavo.-
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Old 12-28-2001, 08:58 AM   #12
Peter
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All the Disconnect related errata are relevant - the Disconnect is what causes the processor to power down. Erratum #14 is the most likely one to bite you.

regards, Peter
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Old 12-28-2001, 11:47 AM   #13
gustavo
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Peter: the errata you suggest ...

14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from Disconnect

Non-conformance: The processor uses a special circuit to wake up from a low-power state and reconnect to the system bus when the nominal operating frequency is generated with a half-frequency multiplier. This circuit is rarely observed to glitch when coming out of the C2 and C3 low-power states.

Potential Effect on System: The system will hang.

Suggested Workaround: Do not use the C2 or C3 ACPI states on processors that run at a nominal operating frequency generated with a half-frequency multiplier. This can be acomplished by having the BIOS not declare C2 or C3 support to the operating system in the Fixed ACPI Description Table (FADT).

Does this suggested workaround mean disabling the HLT command detect ?
I mean I dont know what are the C2 and C3 ACPI states.

Thanks Gustavo.-


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Old 12-28-2001, 03:10 PM   #14
Peter
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Cn are CPU states. C1 is fully powered, C2 and C3 are suspended states. Not supporting the modes in power management is one thing you need to do to get around this erratum, disallowing a disconnect on HLT instruction the other.

regards, Peter
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Old 12-28-2001, 03:37 PM   #15
gustavo
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So Peter, I guess we found here is the answer to the question ?
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Old 12-30-2001, 06:54 AM   #16
gustavo
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Peter: my question is not a rhetorical one, is that i am really not sure of having understood the subject correctly, I am not a technician
on the subject and there is even the tongue problem to me, you glad people in this world that have the fortune of being english speaking
please dont forget us that use other lenguages and have to take extreme care trying not to misunderstand so delicated issues.

Regards Gustavo.-
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Old 12-30-2001, 07:53 AM   #17
Peter
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Well I'm not a native English speaker either ... but anyway. Issues #11 and #14 are the reasons why you want to keep a T-Bird
or Duron from doing a Disconnect - i.e. you don't want it to power down on a HLT command, and you don't want to initiate
a CPU powerdown from the chipset either.

regards, Peter
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Old 12-31-2001, 03:49 AM   #18
gustavo
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Many thanks Peter, I appreciate very much your patience, tolerance and good willing to help me understand the issue. I keep wondering why however this is not so widely known and a concern to many AMD users that do worry about their cpu temp.

My system has not hung so far having set HLT detect enable 2 weeks ago with wpcrset and runs a lot cooler, even using a half frequency multiplier cpu (7.5 * 133). Before having set the bit the cpu temp reached easily 50C idle on summer days, now after running a cpu intensive application the maximum I have seen is 46C.

Would you give me an advice (or personal opinion) , would you keep the bit set ?

Anyway thank you Peter, have a Happy New year (dont know your time, mine is Greenwich - 3)
Gustavo.-
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Old 12-31-2001, 04:17 AM   #19
Peter
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I'd buy a Palomino core CPU Seriously, there is no need to worry about temperatures. The Athlon core is allowed 95 degrees Celsius. Power consumption wise, I'd at least follow the advice of not enabling it for those with fractioned multiplier.

regards, Peter
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Old 12-31-2001, 07:07 AM   #20
gustavo
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Thanks again Peter.

I wonder what is like the temperature of a PC monitor electronic components, it has been my curiosity since I know of the AMD processors temperature being higher than Intel ones and the maximum temp an electronic circuit can withstand.

I mean, if you touch the upper surface of a monitor case you can feel much heat that even touching the cpu dissipator.

Do you have any rough idea ?

Thanks Gustavo.-
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Old 01-31-2002, 08:41 AM   #21
gustavo
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follows ...
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Old 01-31-2002, 08:43 AM   #22
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Peter: if it were so simple and no secret info wortwhile to hide why I got this response from AMD .....



<< Hello Gustavo,

Thank you for contacting AMD. My name is Jay Taylor and I am the Supervisor of our Technical Service Center. While I understand your desire to know and understand this issue, unfortunately this info is confidential and only available under a Non Disclosure Agreement at this time. We are working with our product line to determine what information can be released to the public, however until the appropriate determinations have been made, Ryan, myself, nor anyone else at AMD can comment on this topic. We appreciate your patience. If you would like to arrange for an NDA, please contact your local AMD sales office and they can advise you of the appropriate requirements for an NDA. You can find the office nearest you on our web at:

http://www.amd.com/us-en/Processors/...59_710,00.html

Please understand that AMD reserves the right to determine what information is disclosed to the public.

Respectfully,
Jay Taylor
Supervisor / Apps. Engineer
AMD


-----Original Message-----
From: Gustavo
Sent: Thursday, January 17, 2002 10:08 AM
To: Gardner, Ryan
Subject: RE: ERRATA PREVENTING HLT DETECT ENABLING AT THE BIOS LEVEL??
Importance: High


Ryan: please is there an issue ?
Is there a problem ?
I am just asking why all socket A mainboards have HLT detect disabled.

Please need your answer, "I dont know" could be your answer but no way "I cannot comment on this issue" you
are the technical support, give me the correct e-mail address then, but be serious.

Gustavo.-

-----Mensaje original-----
De: ryan.gardner@amd.com [mailto:ryan.gardner@amd.com]
Enviado el: mi&eacute;rcoles, 16 de enero de 2002 16:03
Para: Gustavo
Asunto: RE: ERRATA PREVENTING HLT DETECT ENABLING AT THE BIOS LEVEL??


Hello,

Again, please be patient. You will receive a response. I am unfortunately unable to comment on this issue.

Regards,

Ryan Gardner
CPU Specialist
AMD
TSC


-----Original Message-----
From: Gustavo
Sent: Wednesday, January 16, 2002 10:29 AM
To: Gardner, Ryan
Subject: RE: ERRATA PREVENTING HLT DETECT ENABLING AT THE BIOS LEVEL??


An official response ?
What do you mean ?

Gustavo.-

-----Mensaje original-----
De: ryan.gardner@amd.com [mailto:ryan.gardner@amd.com]
Enviado el: mi&eacute;rcoles, 16 de enero de 2002 15:20
Para: Gustavo
Asunto: RE: ERRATA PREVENTING HLT DETECT ENABLING AT THE BIOS LEVEL??


Hello Gustavo,

Again, we appreciate your patients. However, our product line will be developing an official response to your question. Please stay posted for more information.

Regards,

Ryan Gardner
CPU Specialist
AMD
TSC




-----Original Message-----
From: Gustavo
Sent: Wednesday, January 16, 2002 10:00 AM
To: Support15, HW
Subject: RV: ERRATA PREVENTING HLT DETECT ENABLING AT THE BIOS LEVEL??
Importance: High


So please if you dont know redirect me again Ryan ......

Ryan:

Richard give me your e-mail to address this question I am asking AMD since december 28, "Why all socket A motherboard BIOSes disable HLT Detect. " I asked MSI (the manufacturer of my motherboards) to realese a new BIOS with HLT detect enabled and they responded "AMI
and AWARD were asked by AMD to disable it and therefore will not be enabling the option".

So is there any Athlon errata preventing to enable HLT detect at the BIOS level ? If there is one, where can I find the information regarding the errata ? Please just a simple answer for a simple question.

Please: the documentation I downloaded from your web site at:
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_756_759^2983,00.html

Describes exactly the process of Power Management for the Athlon Processor Model 4:
>>




:disgust:
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Old 01-31-2002, 08:48 AM   #23
Shalmanese
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There hands are tied, they cant tell you anything more.
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Old 01-31-2002, 10:06 AM   #24
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thats what I was referring to.... vcool hard-locks my machine if I enable bus disconnects, and the author said AMD wasn't willing to give out the needed doc. the one needed gives precise (updated) timing information that you need to get the chip out of low-power mode properly
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Old 01-31-2002, 02:06 PM   #25
Peter
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... yet still, those Athlons and Durons that have fractioned multipliers won't wake up right even when following these non-disclosed new timing specifications. This is in the published errata document.

regards, Peter
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