Intel "Haswell" Speculation thread

[sm625]

Well I for one am tired of my desktop pumping out heat like its a space heater. And mine is only pulling 200 watts from the wall. It is amazing how much heat you get from 200 watts! If haswell can give me the same cpu and gpu performance as my current i5-750 3.4GHz / HD5770, for only 15 watts, then I'd be happy to replace it with a tablet. I seriously doubt it is going to be able to do that. Luckily a 5770 is a bit beyond what I need, so there is a chance that whatever fits into a tablet form will still be enough.

[hoodlum90]

It looks like the GT3 will be only available for Mobile CPUs. I am concerned that Intel is shifting focus to mobile and Xeon cpus while artificially limiting the capabilities of the traditional desktop cpus. We are already seeing this with overclocking and now with graphics as well

http://www.cpu-world.com/news_2012/2...rocessors.html

[Rumpelstiltskin]

Originally Posted by tweakboy

You guys are forgetting.. Haswell will have 6 core 12 threads models for desktop.

I see more then just 5 percent IPC , more like 15 to 25 percent... and throw in quad chanell 2400Mhz memory and a SSD ,, the haswell will pownz us all.

Why does everyone keep saying this? Intel's slides clearly show 2/4 cores for haswell.

[ShintaiDK]

Originally Posted by Rumpelstiltskin

Why does everyone keep saying this? Intel's slides clearly show 2/4 cores for haswell.

Either they are talking about Haswell-E. Or they are just in a dream

Yes, Haswell for mobile and desktop(LGA1150) will be 2 and 4 cores.

[Sweepr]

As long as they keep improving performance end efficiency with higher IPC, clocks, and lower power comsumption each gen I dont see need to release hexa-cores for mainstream users. Higher single-thread performance translates to more performance more often than +cores in client apps.

[Kristijonas]

Originally Posted by Sweepr

As long as they keep improving performance end efficiency with higher IPC, clocks, and lower power comsumption each gen I dont see need to release hexa-cores for mainstream users. Higher single-thread performance translates to more performance more often than +cores in client apps.

Exactly my thoughts.

[Edrick]

Originally Posted by Rumpelstiltskin

Why does everyone keep saying this? Intel's slides clearly show 2/4 cores for haswell.

The people who say it are just talking out of their arse with no proof whatsoever. It is best to just ignore them.

[Rumpelstiltskin]

Is anyone else as excited about this new architecture as I am? Even if the performance only goes up by a small amount, it will introduce and support pretty much all the standards on the road map for the foreseeable future. I can't think of a better reason to upgrade, as it will likely last you many many years before retiring.

[thm1223]

Originally Posted by Rumpelstiltskin

Is anyone else as excited about this new architecture as I am? Even if the performance only goes up by a small amount, it will introduce and support pretty much all the standards on the road map for the foreseeable future. I can't think of a better reason to upgrade, as it will likely last you many many years before retiring.

Pardon my ignorance, but could you explain what you mean by "it will introduce and support pretty much all the standards on the road map for the foreseeable future"?

Also, don't most processors that have come out in the last few years fall under the "it will likely last you many many years before retiring" category?

[Lonbjerg]

Originally Posted by thm1223

Pardon my ignorance, but could you explain what you mean by "it will introduce and support pretty much all the standards on the road map for the foreseeable future"?

Also, don't most processors that have come out in the last few years fall under the "it will likely last you many many years before retiring" category?

Google AVX2...

[BenchPress]

Originally Posted by Lonbjerg

Google AVX2...

...and HLE, RTM, BMI2, FMA3...

[Pr0d1gy]

I am absolutely looking forward to Haswell. My last processor was an FX-55, so I imagine this will be like going from dial-up to broadband....lol

The best part is I plan on building a new gaming/multimedia PC with my tax returns and reports indicate that is exactly when Haswell is being released.

[Hugo Drax]

Originally Posted by hoodlum90

It looks like the GT3 will be only available for Mobile CPUs. I am concerned that Intel is shifting focus to mobile and Xeon cpus while artificially limiting the capabilities of the traditional desktop cpus. We are already seeing this with overclocking and now with graphics as well

http://www.cpu-world.com/news_2012/2...rocessors.html

Wow that sucks. The intel GPU works great in Linux. I have a few workstations based on the 3770K and built in GPU running 3.5 kernel.

I would love to see GT3 in the K series chip they release in 2013

[Lonbjerg]

Originally Posted by Hugo Drax

Wow that sucks. The intel GPU works great in Linux. I have a few workstations based on the 3770K and built in GPU running 3.5 kernel.

I would love to see GT3 in the K series chip they release in 2013

I would love for them to rip the IGP far, far away from my CPU's...

[shadow_k]

Does anyone know or have any clue on improvements that 1150 mobo will have over z77?

[Abwx]

Originally Posted by shadow_k

Does anyone know or have any clue on improvements that 1150 mobo will have over z77?

Informations are still scarce about HW.

http://en.wikipedia.org/wiki/Haswell...rchitecture%29

[tynopik]

Originally Posted by shadow_k

Does anyone know or have any clue on improvements that 1150 mobo will have over z77?

Haswell support

cheaper (theoretically)

MAYBE true triple monitor support for the IGP

otherwise everything stays where it is: USB3, PCIe 3.0, SATA3, DDR3, etc

[pantsaregood]

Just saw on Wikipedia that Haswell is expected to have an L2 Trace Cache. If it does, what exactly does this entail?

I know NetBurst employed an L1 Trace, but I don't really know how that affected performance.

[ShintaiDK]

Originally Posted by shadow_k

Does anyone know or have any clue on improvements that 1150 mobo will have over z77?

The 8 series chipset aint changed much (And why would it?). You basicly get more SATA6 ports and more USB3.

Else a big change is the ondie VRM. So you will notice motherboards looking quite different.

[BenchPress]

Originally Posted by pantsaregood

Just saw on Wikipedia that Haswell is expected to have an L2 Trace Cache. If it does, what exactly does this entail?

I know NetBurst employed an L1 Trace, but I don't really know how that affected performance.

That expectation seems a bit sketchy. First of all Sandy/Ivy Bridge doesn't have a trace cache but a uop cache, and going back to a NetBurst-style trace cache for Haswell is extremely unlikely.

Even if we assume they meant an L2 uop cache, it still doesn't make a whole lot of sense. Uops are relatively big, and the purpose of the uop cache is to lower the branch misprediction latency and save on decoding power. Missing the L1 uop cache and having to access an L2 uop cache adds latency, so there's probably no gain there. And the L1 uop cache already has a hit rate of 80% so an L2 uop cache wouldn't significantly lower the decoder activity either. Besides, the uop cache is really more like an L0 instruction cache. So I don't see where another cache level would fit in.

The only thing I can imagine is that the L1 instruction cache would contain predecoding information. It would lower the branch misprediction latency by a bit and potentially save some power. More importantly this could also allow them to perform macro-op fusion between a mov and an arithmetic instruction. The predecoder could check for operand dependencies in a power efficient way since it wouldn't be pressed for time if it sits between the L2 and L1 cache. It also saves uop cache space since they are non-destructive already.

This would improve Haswell's scalar IPC by several percent.

[Hugo Drax]

Originally Posted by BenchPress

That expectation seems a bit sketchy. First of all Sandy/Ivy Bridge doesn't have a trace cache but a uop cache, and going back to a NetBurst-style trace cache for Haswell is extremely unlikely.

Even if we assume they meant an L2 uop cache, it still doesn't make a whole lot of sense. Uops are relatively big, and the purpose of the uop cache is to lower the branch misprediction latency and save on decoding power. Missing the L1 uop cache and having to access an L2 uop cache adds latency, so there's probably no gain there. And the L1 uop cache already has a hit rate of 80% so an L2 uop cache wouldn't significantly lower the decoder activity either. Besides, the uop cache is really more like an L0 instruction cache. So I don't see where another cache level would fit in.

The only thing I can imagine is that the L1 instruction cache would contain predecoding information. It would lower the branch misprediction latency by a bit and potentially save some power. More importantly this could also allow them to perform macro-op fusion between a mov and an arithmetic instruction. The predecoder could check for operand dependencies in a power efficient way since it wouldn't be pressed for time if it sits between the L2 and L1 cache. It also saves uop cache space since they are non-destructive already.

This would improve Haswell's scalar IPC by several percent.

You should go and work at Intel.

assuming you don't already work there.

[bronxzv]

@BenchPress not directly related to this post but to a past discussion of ours about the MIC-AVX convergence, one more clue it's coming: http://software.intel.com/en-us/forums/showpost.php?p=190704

"Reconciliation of MIC instruction sets with future AVX is a publicized goal"

[oceanside]

Originally Posted by Pr0d1gy

I am absolutely looking forward to Haswell. My last processor was an FX-55, so I imagine this will be like going from dial-up to broadband....lol

The best part is I plan on building a new gaming/multimedia PC with my tax returns and reports indicate that is exactly when Haswell is being released.

Well, I'm sending this P4(478)Prescott out to pasture when Haswell comes out. Unless they decide to keep the paste under the IHS like Ivy. Then I may decide to vote with my dollar and support the underdog. Say what you want about Prescotts... at least they have a soldered lid. Lasted a good long time of faithful service over the years of daily use.

[ShintaiDK]

Originally Posted by oceanside

Well, I'm sending this P4(478)Prescott out to pasture when Haswell comes out. Unless they decide to keep the paste under the IHS like Ivy. Then I may decide to vote with my dollar and support the underdog. Say what you want about Prescotts... at least they have a soldered lid. Lasted a good long time of faithful service over the years of daily use.

So you base your buy on whatever paste is used, seriously?

[BenchPress]

Originally Posted by bronxzv

not directly related to this post but to a past discussion of ours about the MIC-AVX convergence, one more clue it's coming: http://software.intel.com/en-us/forums/showpost.php?p=190704

"Reconciliation of MIC instruction sets with future AVX is a publicized goal"

Awesome. Thanks for the heads up.