big.LITTLE: the death of Medfield

[Exophase]

David Kanter once assured me that Intel would be at no density disadvantage with their 32nm SoC process vs TSMC's 28nm LP process. Of course, that was merely his take and I'm not sure how heavily it was investigated; it was also before any products appeared on TSMC's 28nm. He more or less conceded that TSMC had a density advantage on its 40nm vs Intel's 45nm, but said that it was because TSMC had looser layout restrictions and that this would change with 28nm. We've seen very good scaling of similar products from their 40nm to 28nm so I don't know how much this was proven true. But I'm also not very knowledgeable of this process stuff :/

For what it's worth, I always got the impression that the density on Samsung's 45nm wasn't very good either.

[Exophase]

Originally Posted by GillyBillyDilly

Care to be a bit more concrete?

1 - If you have been following this thread, you'd know my stand on the big little and power scaling approaches.

Your stance on big.LITTLE seems to be "no sir, I don't like it." If you have a good technical argument on why it shouldn't be used I'm not seeing it, sorry..

That doesn't mean it's the future or everyone should use it or it's not a compromise. Time will tell if it becomes a common thing or is marginalized. Just because Intel and Qualcomm aren't currently doing it or anything similar doesn't mean it'll be snubbed out. Companies do have a tendency to chastise technologies that they're not adopting. ARM criticized SMT (which many use, not just Intel), and I don't really agree with their stance..

It's really not just ARM looking at coherent heterogeneous cores. Marvell announced one such solution years ago, although they didn't give a lot of details and it doesn't look like it has materialized (at least not yet). Some were speculating that ARM would offer such a thing themselves well before big.LITTLE was announced - for instance read the Beyond3D ARM article Arun wrote, where he says he anticipates this being the next big move for ARM, and mentioned the possibility of an A15 + A5 configuration (this was before A7 was announced). And no, he didn't have any kind of industry tips on this.

This was well before anyone could really give good speculation on A15's perf/W profile, although those who looked at it sincerely tended to agree that the perf/W would be worse than A9 on a similar process node, at least in the higher perf ranges. That's why ARM doesn't just offer big.LITTLE but a wide variety of cores optimized for different perf/W and peak perf levels. In the same way A57 is a successor to A15 and A53 a successor to A7 it wouldn't be that weird if we saw something target a level in between, although ARM might have to scale down the number of A-series cores they can design now that they're losing more big volume licensees for these cores.

[IntelUser2000]

Originally Posted by Exophase

For what it's worth, I always got the impression that the density on Samsung's 45nm wasn't very good either.

No, it isn't. I assume density wise from best to last its: TSMC, Intel, everyone else.

I think while Intel is second to none when talking about their Core design teams and process and looking at all metrics, performance, perf/watt, perf/area, those looking purely from a density perspective or Intel as a foundry, they are probably behind TSMC.

It's to be seen how good the Atom team can be when 22nm arrives. Although I think ultimately, the real good chip will be when the results of the supposed Atom/Core team collaboration shows up. And we do not know if that's the 22nm Atom, or later.

Also for the topic: One PCWatch article is showing that the "Dual core" version of Silvermont is actually 1 Medfield + 1 Merrifield core. And the quad core is 2 Medfield + 2 Merrifield. If that's the truth, Intel may have their version of small core + big core in similar timeframe to ARM's big.LITTLE. The only question is if PCWatch merely made a mistake or they leaked something critical without realizing.

[ShintaiDK]

Originally Posted by IntelUser2000

Also for the topic: One PCWatch article is showing that the "Dual core" version of Silvermont is actually 1 Medfield + 1 Merrifield core. And the quad core is 2 Medfield + 2 Merrifield. If that's the truth, Intel may have their version of small core + big core in similar timeframe to ARM's big.LITTLE. The only question is if PCWatch merely made a mistake or they leaked something critical without realizing.

Could you link that? Neither Medfield or Merrifield is a core name either. Its a package name.

Not to mention Medfield is 32nm and Merrifield is 22nm.



And something interesting:

[Exophase]

Originally Posted by IntelUser2000

I think while Intel is second to none when talking about their Core design teams and process and looking at all metrics, performance, perf/watt, perf/area, those looking purely from a density perspective or Intel as a foundry, they are probably behind TSMC.

Personally, given what information we have, I'd easily rate Apple's Swift core as in A6 as a better core than Saltwell. Yes, Intel still beats it in Javascript tests, but you all know how I feel about those. I expect that at 1.4GHz it will generally perform better than Saltwell at 1.8GHz under reasonable hardware evaluation conditions. And it's using much less power while doing so. Seeing as how Clover Trail and dual core Kraits are pretty competitive in both perf and power, and how A6 pretty clearly beats those Kraits in both.

Area is also at least as good. Part of this is a testimony that Samsung's 32nm HKMG is at least not bad, and it does at least give a big density improvement over their 45nm (higher than you often see elsewhere).

I do think you raise an interesting point - for some applications like big GPUs a big density advantage can quickly turn into a big perf and perf/W advantage.

Originally Posted by IntelUser2000

Also for the topic: One PCWatch article is showing that the "Dual core" version of Silvermont is actually 1 Medfield + 1 Merrifield core. And the quad core is 2 Medfield + 2 Merrifield. If that's the truth, Intel may have their version of small core + big core in similar timeframe to ARM's big.LITTLE. The only question is if PCWatch merely made a mistake or they leaked something critical without realizing.

I'd be pretty shocked if this were the case, although it's perhaps the most plausible solution Intel would have for a big.LITTLE-like arrangement. Still, does Intel really want to shrink Saltwell?

AFAIK Silvermont is the CPU core (vs Saltwell) and Merrifield the SoC.. and stuff like Penwell refers to a platform including SoC + other chips. So this would mean Merrifield contains two Silvermont cores and two Saltwell-derived cores. I say Saltwell-derived because they'd surely have a different name, since they're shrunk, much like Saltwell itself isn't that much than a shrink of Bonnell (at least in functional behavior)

But I can't keep these damn code names straight at all so I could be wrong here. Neither with AMD, they're so numerous.

[IntelUser2000]

Yes, you are right, I couldn't remember the core code names straight off my heard, so I went with a platform one.

Saltwell + Silvermont was for dual cores, and 2x Saltwell + 2x Silvermont was for quad cores.

I'd easily rate Apple's Swift core as in A6 as a better core than Saltwell.

Samsung's density is behind, but their 32nm process uses High-K, and probably helps them lower leakages, which helps light load and idle.

A6 is a really good core, but everything being under one roof gives an advantage there as well. I attribute to the A6-based platform having the lowest idle power to that.

for some applications like big GPUs a big density advantage can quickly turn into a big perf and perf/W advantage.

That's changing at Intel for 22nm, with little less focus on peak drive current for things like lower voltages, and better performance at those lower voltages.

The first indication is with Haswell's iGPU. GT2 with 20EUs clocks at 1.15-1.3GHz but GT3 with 40EUs clocks at maybe 900MHz-1GHz.

[Nemesis 1]

Intel has the Z2580 2core phone just released Like the Lenovo K900. They also released a new low end phone to the 3rd world markets .Latter this year intel will release these with products by the holidays .
http://www.engadget.com/2013/01/07/i...tom-bay-trail/

[GillyBillyDilly]

Originally Posted by Exophase

Your stance on big.LITTLE seems to be "no sir, I don't like it." If you have a good technical argument on why it shouldn't be used I'm not seeing it, sorry..

That doesn't mean it's the future or everyone should use it or it's not a compromise. Time will tell if it becomes a common thing or is marginalized. Just because Intel and Qualcomm aren't currently doing it or anything similar doesn't mean it'll be snubbed out. Companies do have a tendency to chastise technologies that they're not adopting. ARM criticized SMT (which many use, not just Intel), and I don't really agree with their stance..

It's really not just ARM looking at coherent heterogeneous cores. Marvell announced one such solution years ago, although they didn't give a lot of details and it doesn't look like it has materialized (at least not yet). Some were speculating that ARM would offer such a thing themselves well before big.LITTLE was announced - for instance read the Beyond3D ARM article Arun wrote, where he says he anticipates this being the next big move for ARM, and mentioned the possibility of an A15 + A5 configuration (this was before A7 was announced). And no, he didn't have any kind of industry tips on this.

This was well before anyone could really give good speculation on A15's perf/W profile, although those who looked at it sincerely tended to agree that the perf/W would be worse than A9 on a similar process node, at least in the higher perf ranges. That's why ARM doesn't just offer big.LITTLE but a wide variety of cores optimized for different perf/W and peak perf levels. In the same way A57 is a successor to A15 and A53 a successor to A7 it wouldn't be that weird if we saw something target a level in between, although ARM might have to scale down the number of A-series cores they can design now that they're losing more big volume licensees for these cores.

Sorry for the delay. I wasn't following this thread any more.

Why I don't like this big little concept? For many reasons, most of which are not relevant in this forum, a couple of those which are:
A core should be able to self regulate it's power usage. Once you move in this direction you learn more and more how to further develope this capability and consequently reach levels of efficiency which are not possible with such approaches as big little. In humans one brain does it all and I think this should be the ultimate goal and principle of the chip industry as well, and not going after any solution which tempts with its apparent ease of implementation.

[krumme]

Originally Posted by Exophase

David Kanter once assured me that Intel would be at no density disadvantage with their 32nm SoC process vs TSMC's 28nm LP process. Of course, that was merely his take and I'm not sure how heavily it was investigated; it was also before any products appeared on TSMC's 28nm. He more or less conceded that TSMC had a density advantage on its 40nm vs Intel's 45nm, but said that it was because TSMC had looser layout restrictions and that this would change with 28nm. We've seen very good scaling of similar products from their 40nm to 28nm so I don't know how much this was proven true. But I'm also not very knowledgeable of this process stuff :/

For what it's worth, I always got the impression that the density on Samsung's 45nm wasn't very good either.

TSMC 40nm had a ~1.78 times higher density than Intel 45nm.
http://www.chip-architect.com/news/2...tels_Atom.html

We discussed it at SA over a year back, and Hans de Vries led us to the equipment used. TSMC simply had newer lithography equipment with stricter tolerances as i rember it. So Kanter was vrong about the looser layout restrictions vs. 45nm Intel - even if that was the story that was told - It was Intel PR at work. Sorry cant find links any more, and probably the numbers wouldnt make sense to me today :=)

(edit: i think the discussion about the equipment used was somewhere around here http://semiaccurate.com/forums/showp...&postcount=139
)

[Homeles]

Plus, TSMC was using gate first back then.