Quote:
Originally Posted by Haserath
Intel already needs something like quad patterning for 22nm. Wouldn't that take up more space than single patterning EUV?
Thus more machines could equal more throughput.
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The space is one issue but it is not THE issue. Space is a one time cost adder when you build the fab and buy the extra tools, and that upfront cost adder depreciates over time.
Rather, THE issue is cycle time and yield loss. Those are the gifts that keep on giving.
Every wafer experiencing longer cycle time and higher yield loss regardless whether it is the first wafer produced on the node or the last wafer produced 10yrs later is a huge aggregate cost adder to the node's cost structure.
The power issue for EUV is kind of a red herring argument for delaying the adoption of EUV. The primary issue with EUV is its cost, and right now the most convenient way to reduce the cost-hit by an EUV tool is to boost throughput (without substantially boosting cost even further) such that the customer need buy as few of them as possible.
Quad patterning is a viable production path because it is cost-competitive with EUV at EUV's current cost/throughput.
The only way EUV can tip that cost/throughput in its favor is if it boosts the throughput number, which is where the throughput roadmap itself came from. The targets on the roadmap aren't a wish list, they are minimum requirement for commercial viability versus known/established market alternatives that would represent comparable cost structure.
