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Old 01-18-2013, 12:48 PM   #1
Phynaz
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Default Who do you think it is?

EE Times is reporting that an unnamed company has 450mm wafer machinery in place. This is expected to cut two years off the industry transition to 450mm wafers.

http://www.eetimes.com/electronics-n...s-450-mm-first

Who do you think this unnamed company is?
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Old 01-18-2013, 12:51 PM   #2
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Intel

D1X M1 and M2 plus Fab42 are directly constructed for 450mm.
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Old 01-18-2013, 12:57 PM   #3
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Given that this is specific to the litho in question - i.e. imprint litho - I would be quite surprised (make that very surprised) if this specific EETimes announcement is actually related to Intel.

TSMC has been a proponent of imprint litho, as has Toshiba. Intel has invested billions into ensuring immersion litho and EUV are its future.

That's not to say that Intel doesn't also have a fully functioning 450mm alpha-tool pilot line setup and running, just saying this particular EETimes article actually leaves me convinced they are not alone in that regard.
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Old 01-18-2013, 01:04 PM   #4
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For half the industry, 450mm gonna be a bloody axe tho. But the sooner we get it the better on the long run.
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Old 01-18-2013, 01:13 PM   #5
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No question it will convert even more IDM's into fabless entities, to the benefit of the foundries.

The cost savings all come at the expense of people losing their jobs though. This is not a growing industry in terms of job growth.

More like a shell game where the same jobs disappear in one place only to re-appear elsewhere, only when they reappear there tends to be fewer of them.

2001 was bloody, as was 2008. 2015 or 2016 is the next wave.
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Old 01-18-2013, 01:51 PM   #6
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Thanks for the reply IDC, I was hoping you would give us your insight.
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Old 01-18-2013, 02:37 PM   #7
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From the same site....

http://www.eetimes.com/electronics-n...ped-to-Toshiba
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Old 01-18-2013, 03:23 PM   #8
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Quote:
Originally Posted by Abwx View Post
Toshiba, yeah that adds up. I'm glad to hear it too, litho is ripe for a disruptive technology, EUV is silly expensive and has taken a decade plus to even get to its currently unacceptable price-point. Imprint litho is not the golden solution, but at least it is disruptive enough to possibly kickstart something that will be.

Moore's Law is one of economics, not physics and not technology. And conventional litho (including EUV) is killing the economics of continuing Moore's Law.
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Old 01-18-2013, 03:46 PM   #9
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Perhaps almost good enough for products that have intrinsical
high redundancy such that defect density is almost
neutralized , the component of choice being ram chips.
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Old 01-19-2013, 02:02 AM   #10
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The narrow scope of the actual business term disruptive is dead I see.
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Old 01-19-2013, 02:49 AM   #11
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What makes EUV so expensive?
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Old 01-19-2013, 07:05 AM   #12
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Quote:
Originally Posted by Soleron View Post
The narrow scope of the actual business term disruptive is dead I see.
http://www.youtube.com/watch?v=3pwvB4_Te8A

Quote:
Originally Posted by Haserath View Post
What makes EUV so expensive?
http://www.eetimes.com/electronics-n...t--120-million-

Quote:
Who can afford extreme ultraviolet (EUV) lithography?

Answer: Very few companies. And the tool price tag is going up. ''EUVL: and the price is? The answer is...$125 million'' per tool, said G. Dan Hutcheson, CEO of VLSI Research Inc., in a report.

But EUV has been delayed and R&D costs have exploded, causing tool costs to soar out of control. An ''alpha'' EUV tool from ASML Holding NV went for a reported $60 million per unit.
EUV is expensive because there is a mountain of R&D expenses that have been invested into EUV and those expenses must be recaptured in the sale of the tools.

Sell only 10 tools and they will cost you $500m each, sell 100 tools and they might only cost you $100m each.

It is the exact same market economics at work which result in $2B stealth planes and so forth. The cost to produce the widget is not simply the production cost, you have to recapture the development cost.

Which means the question is not "what makes EUV so expensive?"; rather, the question one really means to ask is "what makes EUV development so expensive?"

And the answer to that comes down to the customer's requirements on the tool's capabilities. Wafer throughput, defectivity, lifetime reliability, etc.

In other words, we are right back to the unavoidable consequences of the math that are captured by the Project Management Triangle.



^ you can pick any 2 of the 3, but no more than 2.

The customers want all 3, naturally. But when asked to prioritize them they all insist on EUV being fast (competitive wafer throughput) and good (competitive defectivity, alignment, etc) and that means "cheap" is not happening at time-zero.

Cheap will happen, as more tools are sold over time the price per unit will decrease as EUV tool makers (ASML) recapture a higher and higher percentage of their development costs.

It is very similar to what makes the first few ten thousand 28nm wafers at TSMC cost $7k, but now a year later they only cost $2.5k.
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Old 01-19-2013, 02:28 PM   #13
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Thanks IDC
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Old 01-20-2013, 10:23 AM   #14
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http://www.xbitlabs.com/news/other/d...er_Photos.html



Intel is expected to start 450mm production in 2015.
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Old 01-20-2013, 12:04 PM   #15
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Quote:
Originally Posted by ShintaiDK View Post
http://www.xbitlabs.com/news/other/d...er_Photos.html



Intel is expected to start 450mm production in 2015.
Quote:
This wafer was created after intense collaboration which was necessary between Intel and various suppliers, three of whom are Sumco, Dainippon Printing and Molecular Imprints, according to Intel.
Well then, looks like I was completely in the wrong about the prospects of the OP having something to do with Intel. That 450mm imprint litho tool could have very well been delivered to Intel after all
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Old 01-20-2013, 01:53 PM   #16
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Old 01-20-2013, 04:20 PM   #17
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Quote:
Originally Posted by ShintaiDK View Post
http://www.xbitlabs.com/news/other/d...er_Photos.html


Intel is expected to start 450mm production in 2015.
It's funny the first time I looked at that photo I thought they were displaying a broken wafer. Upon closer inspection I realized the broken edge was actually his reflection. I must have tired eyes today.
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Old 01-20-2013, 06:44 PM   #18
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Quote:
Originally Posted by ShintaiDK View Post
http://www.xbitlabs.com/news/other/d...er_Photos.html



Intel is expected to start 450mm production in 2015.
More info from the link:

Quote:
At the SEMI Industry Strategy Symposium (ISS) this week Intel demonstrated a 450mm wafer that is fully patterned for the first time. This wafer was created after intense collaboration which was necessary between Intel and various suppliers, three of whom are Sumco, Dainippon Printing and Molecular Imprints, according to Intel.

“It is an important step forward and it indicates that there will soon be substantial volume of patterned test wafers for use by suppliers in developing their 450mm tools,” explained Chuck Mulloy, a spokesman for Intel during a conversation with X-bit labs.


Bob Bruck (left), Intel vice president of technology manufacturing engineering (TME), unveiled the first fully patterned 450mm wafer January 15 at the SEMI Industry Strategy Symposium with Intel's Mario Abravanel. Image by Intel.

No public details about the wafer have been revealed officially. A report claims that Molecular Impints’s Jet and Flash (J-Fil) imprint lithography technology has demonstrated 24-nm patterning with line edge roughness of less than 2nm to 3sigma and critical dimension uniformity to 1.2nm 3sigma and offers the prospect of 10nm patterning with single-step process.
Sounds like a lot of detail is still under wraps.

Hmmmm.....would be interesting to find out if the expansion of D1X has anything to do with Nano imprint?
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Old 01-20-2013, 06:50 PM   #19
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Quote:
Originally Posted by GreenChile View Post
It's funny the first time I looked at that photo I thought they were displaying a broken wafer. Upon closer inspection I realized the broken edge was actually his reflection. I must have tired eyes today.
LOL, me too! I did a double-take on that until I realized it was the dude's shadow that was giving that appearance.
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Old 01-20-2013, 07:00 PM   #20
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Quote:
Originally Posted by Idontcare View Post


EUV is expensive because there is a mountain of R&D expenses that have been invested into EUV and those expenses must be recaptured in the sale of the tools.

Sell only 10 tools and they will cost you $500m each, sell 100 tools and they might only cost you $100m each.

It is the exact same market economics at work which result in $2B stealth planes and so forth. The cost to produce the widget is not simply the production cost, you have to recapture the development cost.

Which means the question is not "what makes EUV so expensive?"; rather, the question one really means to ask is "what makes EUV development so expensive?"

And the answer to that comes down to the customer's requirements on the tool's capabilities. Wafer throughput, defectivity, lifetime reliability, etc.

In other words, we are right back to the unavoidable consequences of the math that are captured by the Project Management Triangle.



^ you can pick any 2 of the 3, but no more than 2.

The customers want all 3, naturally. But when asked to prioritize them they all insist on EUV being fast (competitive wafer throughput) and good (competitive defectivity, alignment, etc) and that means "cheap" is not happening at time-zero.

Cheap will happen, as more tools are sold over time the price per unit will decrease as EUV tool makers (ASML) recapture a higher and higher percentage of their development costs.

It is very similar to what makes the first few ten thousand 28nm wafers at TSMC cost $7k, but now a year later they only cost $2.5k.
Yep, and it sure seems (at least by my understanding) that the power requirement for each node keeps increasing.

So to get 60 wph at 7nm will take more power than 60 wph at 10nm.

I keep looking for Press releases on the EUV power source development and haven't seen anything new.

My guess is that in order for ASML/Cymer to convince Intel that EUV will be ready for 7nm some type of believable power scaling progression will need to be developed in order to hit the window at 7nm. (Last time I checked Cymer were at a sustainable 30 watts, but in order to get 7nm throughput at a decent speed they will need much more than that!)

See ASML roadmap for example of how the power requirement scales:



16nm at 180 wph needs 500 watts. This makes me wonder what 7nm will need?
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Old 01-20-2013, 07:21 PM   #21
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Originally Posted by Computer Bottleneck View Post
Yep, and it sure seems (at least by my understanding) that the power requirement for each node keeps increasing.

So to get 60 wph at 7nm will take more power than 60 wph at 10nm.

I keep looking for Press releases on the EUV power source development and haven't seen anything new.

My guess is that in order for ASML/Cymer to convince Intel that EUV will be ready for 7nm some type of believable power scaling progression will need to be developed in order to hit the window at 7nm. (Last time I checked Cymer were at a sustainable 30 watts, but in order to get 7nm throughput at a decent speed they will need much more than that!)

See ASML roadmap for example of how the power requirement scales:



16nm at 180 wph needs 500 watts. This makes me wonder what 7nm will need?
It is a rather disconcerting situation
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Old 01-20-2013, 07:28 PM   #22
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Quote:
Originally Posted by Computer Bottleneck View Post
This makes me wonder what 7nm will need?
2000-2400 watts.
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Old 01-26-2013, 02:39 AM   #23
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EUV update--

http://optics.org/news/4/1/26

Quote:
Originally Posted by Optics.org 1/20/2013
We are encouraged by the latest EUV development performance as we have now demonstrated a stable 40 W of EUV source power against a production target of 105 W,” said CEO Meurice, adding that the source design had now been tested successfully at up to 60 W for debris mitigation and had shown no signs of performance degradation.
Source power gets a bump to 40 watts from the stable 30 watts it was at Summer 2012 (see below) --> http://www.eetimes.com/electronics-n...e-EUV-together

Quote:
Originally Posted by EE Times 10/17/2012
ASML and Cymer jointly made significant progress during the summer and have now proven in laboratories a sustained 30-Watt source exposure power potential
Now if they can only get that 33% increase in stable power every six months....they would actually have a good amount of power by the time Intel's 7nm or 5nm node rolls around.

Last edited by cbn; 01-26-2013 at 02:43 AM.
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Old 01-26-2013, 04:22 AM   #24
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15mJ/cm^2

So Haswell would receive around a whopping 30mJ per full die?

Anybody know the current wafer throughput and wattage?
Quote:
16nm at 180 wph needs 500 watts. This makes me wonder what 7nm will need?
For the same wph, wouldn't it only need around 1100-1200W? I don't really know if that's all that high really...

Last edited by Haserath; 01-26-2013 at 04:34 AM.
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Old 01-26-2013, 04:53 AM   #25
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Intel already needs something like quad patterning for 22nm. Wouldn't that take up more space than single patterning EUV?

Thus more machines could equal more throughput.
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