Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

That should finally bring more modularity / re-useability to client PCs, and hopefully, faster release cycles. And maybe even a greater range of SKUs.

Not quite but it does enable more direct IP sharing between DT and mobile or ultrathin and luggable depending on your definition.

If they do tiled HSIO, possibilities extend though.
Like a luggable core/SOC but HSIO is loaned from the premium ultrathin 28W part so it gets USB4s and all.
Dunno if they're gonna do that, though.

 

[itsmydamnation]

Yeah it's all one thing.
That's the idea.

Not seems, that was the OG definition.

culled for time frame or cost/throughput/defect rate or both?

 

[adroc_thurston]

culled for time frame or cost/throughput/defect rate or both?

The former two iirc plus overall fanout capacity.

 

[PJVol]

Strix Point Next Gen AI PC is what Papermaster is mainly hinting at

I'm more interested in the extent to which AI is related to the architecture itself, rather than it being the specific compute block a-la FPGA.
For example, something like region specific ram access scheduling in the memory controller, or like the instruction scheduling based on occupancy or power prediction.

 

[adroc_thurston]

I'm more interested in the extent to which AI is related to the architecture itself

None.

For example, region specific ram access scheduling, or like the instruction scheduling based on occupancy or power prediction

what

 

[PJVol]

what

US10956044B2 ?

 

[darkswordsman17]

None.

what

I think he thinks that AI is being used to direct the chip, like it has an AI processor to "optimize" how it should schedule and utilize resources within the chips?

US10956044B2 ?

What does that have to do with AI? That's basically the system being aware of the memory subsystem such that it directs things where it makes sense so as to minimize latency. It does self test where it checks the timing and other of the memory subsystem to determine if there's any flaws or degradation (it notes due to manufacturing complexities that areas of the memory might not perform the same - also maybe simply due to the fact that using stacked memory that the chips highest on the stack and subsequently furthest in routing, might have more latency?), and then adjusts based on what it gets in response, and then uses that to inform where to send data (I assume its a form of smart scheduling or registering such that it'd direct based on how sensitive to latency or bandwidth it is).

There's probably some OEMs who will try. But 16 CU + 12 Cores feels wholly inappropriate for a Handheld device.

Then again people are using these while connected at wall charger all the time and full blasting at 45W. To the point that the Handheld aspect basically lost it's meaning

I think for many its more of a single transportable device for all their gaming. Instead of lugging a laptop + controller/mouse they have a smaller device. And for many its also a 2nd screen (so they can game while they're in watching TV, especially if they have other family so are sharing the TV). I don't see it as inherently fundamentally flawed like the Windows handhelds (UMPC?) of like the mid 2000s, or netbooks, but rather just a device focused around gaming (that can do more - which its not optimal for doing, but can do ok and can also serve as a primary PC when docked due to the capabilities of the chip and how much docking can enable these days). I do think the industry that popped up in response (especially the Chinese ones putting out dozens of iterations of these) is silly, but the Switch and Steamdeck show this isn't really a niche market. Also, the ability to use a portable non-portably was apparent to even Nintendo is telling. People clearly want portable gaming devices.

 

[adroc_thurston]

I think he thinks that AI is being used to direct the chip, like it has an AI processor to "optimize" how it should schedule and utilize resources within the chips?

You don't need hallucination machines for that.

 

[Joe NYC]

Not quite but it does enable more direct IP sharing between DT and mobile or ultrathin and luggable depending on your definition.

If they do tiled HSIO, possibilities extend though.
Like a luggable core/SOC but HSIO is loaned from the premium ultrathin 28W part so it gets USB4s and all.
Dunno if they're gonna do that, though.

To serve cost effective markets, the IO could go back to N6. Having memory controllers also on the IO die would allow cost effective MALL cache. If power overhead between CPU CCD and SoC is not too terrible for Strix Halo, then it would be fine for Zen 6 as well.

But if GPU were to be a 3rd tile, then the power overhead between GPU and IO die might be too high for mobile...

One thing that would be fantastic if AMD could merge NPU and GPU, since there is already a lot of overlap... Maybe just call it NPU that can also do graphics, to keep Microsoft happy.

 

[soresu]

You don't need hallucination machines for that.

You don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?

 

[itsmydamnation]

You don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?

Bobcat

 

[adroc_thurston]

You don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?

They still do, two-level overriding BP is still very much AMD's favourite gimmick.

 

[soresu]

They still do, two-level overriding BP is still very much AMD's favourite gimmick.

Oh, I thought that something called a TAGE predictor replaced it.

 

[adroc_thurston]

Oh, I thought that something called a TAGE predictor replaced it.

Augmented.
Slower, but more accurate.

 

[PJVol]

I think he thinks that AI is being used to direct the chip, like it has an AI processor to "optimize" how it should schedule and utilize resources within the chips?

Kind of.

What does that have to do with AI?

Well, I didn't claim it necessarily has, I just gave a bad example, but in general you got the idea correctly.

US20230004185A1 - System and method for controllilng electrical current supply in a multi-processor core system via instruction per cycle reduction - Google Patents

Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing...

patents.google.com

Here is another example, where mentioned "smart firmware" that manages IPC / Frequency throttling based on the electrical current usage:

The above method may be implemented for each of the cores, from the first core to the last core (also referred to herein as “core N”), as suitable. The processor cores may be evaluated for voltage change or “looped” by a smart firmware (that is, firmware made intelligent with advanced computing capability such as artificial intelligent or machine learning, for example) or any suitable algorithm to facilitate repeating the above process to calculate a new voltage value for each of the cores.

 

[DrMrLordX]

Problem is, from the few reviews so far, MTL-U = RPL-U. Even in battery life (Against RPL-U), it's hit or miss depending on the OEM implementation. Here, Bionic claims that the move to Intel 3 will yield 10% PPW improvement over Intel 4 Compute Tile. But is that enough for OEMs to choose ARL-U over the cheaper RPL-U?

Depends on how the OEMs utilize Arrow Lake-U. If it's just Meteor Lake on Intel 3, they have the option of setting lower PL values than with Meteor Lake and achieving the same performance. That lets them skimp on cooling and battery. It might be enough to drive BoM down and make for attractive budget machines. Fighting against that will be the inherent costs associated with packaging. Also is Intel even going to be shipping Raptor Lake-U by that point?

In any case the product won't have compelling performance for end users, certainly not when faced with Kraken.

 

[Ghostsonplanets]

they have the option of setting lower PL values than with Meteor Lake and achieving the same performance. That lets them skimp on cooling and battery. It might be enough to drive BoM down and make for attractive budget machines.

Good points! If OEMs can lower platform costs to offset the SoC cost, it can allow them to offer it at attractive price points.

Fighting against that will be the inherent costs associated with packaging.

Right. This is where I question if we'll see proper, Intel like, volume for ARL-U. By 2025, the majority of their product stack will be using tiled designs and will depend on the level of packaging volume they can do.

Also is Intel even going to be shipping Raptor Lake-U by that point?

Yes. Still shipping RPL-U and also RPL-H as budget alternatives over ARL-U/HX.

In any case the product won't have compelling performance for end users, certainly not when faced with Kraken.

Intel choice for a 5 tiles design with ARL / MTL certainly was...something. It obviously drives up their costs and limits how fast they can ship these. When faced against a simpler, monolithic competitor, Intel can't properly answer it unless they slash their margins once again (They can't).

If I were Gelsinger, I would be fast-tracking Panther Lake in 2025 as fast as possible. It's a much more sane design, it uses their own foundry so to reduce dependency on external and should be way more competitive with AMD across the stock, from U to H. A release of PTL in Summer 2025, with it replacing the expensive ARL designs, would to wonders to clean up Intel line-up.

 

[inquiss]

Good points! If OEMs can lower platform costs to offset the SoC cost, it can allow them to offer it at attractive price points.

Right. This is where I question if we'll see proper, Intel like, volume for ARL-U. By 2025, the majority of their product stack will be using tiled designs and will depend on the level of packaging volume they can do.

Yes. Still shipping RPL-U and also RPL-H as budget alternatives over ARL-U/HX.

Intel choice for a 5 tiles design with ARL / MTL certainly was...something. It obviously drives up their costs and limits how fast they can ship these. When faced against a simpler, monolithic competitor, Intel can't properly answer it unless they slash their margins once again (They can't).

If I were Gelsinger, I would be fast-tracking Panther Lake in 2025 as fast as possible. It's a much more sane design, it uses their own foundry so to reduce dependency on external and should be way more competitive with AMD across the stock, from U to H. A release of PTL in Summer 2025, with it replacing the expensive ARL designs, would to wonders to clean up Intel line-up.

I don't know much about panther lake. It will have to be an incredible uplift against arrow lake to get near AMD's zen 5 lineup. What's known about it?

 

[Ghostsonplanets]

I don't know much about panther lake. It will have to be an incredible uplift against arrow lake to get near AMD's zen 5 lineup. What's known about it?

It's not a big uplift over ARL, so it won't match Zen 5. But it will clean up MTL/ARL tile design mess with a much simpler tile design.

PTL-H will be 4P+8E+4LPE with 12 Xe³(96 EUs) Celestial cores.

PTL-U (As said by Tigerick) will be 4P+4LPE with 4 Xe³ (32 EUs) Celestial cores.

So it will be something nice for Intel. Even if it doesn't compete with Zen 5 in perf.

 

[Mahboi]

I fear for Zen 5 sales.

 

[Markfw]

View attachment 98291
I fear for Zen 5 sales.

Do you mean they will be low ? or high ? or something else ?

 

[Abwx]

Oh, I thought that something called a TAGE predictor replaced it.

There s nothing to be replaced, a perceptron doesnt work out of nothing, it need a learning algorhitm, that is a TAGE prediction algorhitm, aka, Tagged Geometric history length, in other words it use a geometric serie to compute the probability that a branch is taken or not.

 

[reggie_fils_aime]

View attachment 98291
I fear for Zen 5 sales.

I love to fear for things that are going to be unchallenged in consumer and client spaces for almost a full year before the competition puts out something that will almost assuredly be underwhelming

like, Zen 5 is going to release this year - intel claims they're getting Arrow Lake out ASAP, but real competition (and real volume with intel) for Zen 5 won't be until Panther Lake.

 

[Joe NYC]

I love to fear for things that are going to be unchallenged in consumer and client spaces for almost a full year before the competition puts out something that will almost assuredly be underwhelming

like, Zen 5 is going to release this year - intel claims they're getting Arrow Lake out ASAP, but real competition (and real volume with intel) for Zen 5 won't be until Panther Lake.

Someone on Intel thread posted that Panther Lake will be 4+4+4, which sounds like a laptop chip. Not something that would challenge Zen 5 desktop.

 

[Abwx]

Someone on Intel thread posted that Panther Lake will be 4+4+4, which sounds like a laptop chip. Not something that would challenge Zen 5 desktop.

Even if only for laptops it seems underpowered to face Zen 5, even if Strix was to use Zen 4 cores it would still be challenging for Intel given that they seem to remove HT and also due to either the sheer amount of cores in Strix or the augmented IPC relatively to Zen 4 in Kraken.