Recent content by Mopetar

  1. M

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    SMT scaling being lower would imply that they've removed some bottlenecks that previously stalled the hardware thread or otherwise left it unable to utilize the core to a greater extent.
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    Discussion Apple Silicon SoC thread

    Even if they changed nothing else, they'd slowly get there just from node improvements. Their alternative is to keep the clock speeds the same while using less power, but they're already leading in that respect, so they take the performance. There are several ways to go about improving an...
  3. M

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Anyone who tests with SPEC isn't using compiler optimizations for comparing performance across CPUs. They'll use the same GCC binary that every CPU gets.
  4. M

    Discussion Apple Silicon SoC thread

    I'm pretty sure the M5 will be out be then, so that's hardly surprising.
  5. M

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Considering how much they added, and how much larger the core grew, I'm not really sure what they would have left out or deemed infeasible. I really don't see them cutting some magic component (or group of them) that delivers another 8% (or more) IPC on top of what they achieved.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I'm not sure how much a node change would affect IPC. Outside of timing issues and having to possibly run a few parts of the chip slower than they would have liked, the IPC is largely a matter of architecture. If you took an ancient x86 CPU like the original Pentium and ported the design to a...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    At least part of Apple's impressive IPC is that they have lower access times (in cycles) to their cache. If they were to ramp up their clock speeds to the same extent that AMD/Intel use, they'd have to increase the latency on their caches. Performance would possibly increase, but IPC would...
  8. M

    Discussion Apple Silicon SoC thread

    It's just basic math. If you go from one of something to two of something (an increase of one) and can fully utilize the additional thing, you get a 100% increase (i.e. double) performance. Adding one more and going from two to three things only increases the performance by 50% over what could...
  9. M

    Question NVIDIA Project G-Assist

    Let's Plays have existed on YouTube for over a decade now. You don't even need to buy the game either. I'd actually like better AIs in games though. Most strategy games increase difficulty by just giving the AI a bigger head start rather than making them play better or make more intelligent...
  10. M

    Discussion RDNA4 + CDNA3 Architectures Thread

    Or they've still got a lot of RDNA2/3 stock they want to get through. No sense in announcing anything that's still months away that might hurts current sales.
  11. M

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Apparently I woke up on the darkest timeline side of the bed today since I've learned that MLID was apparently correct. Tech bros, I'm not feeling so well right now.
  12. M

    Discussion Apple Silicon SoC thread

    It's hardly surprising that everyone is struggling to increase IPC given that everyone has a wider architecture. It's just simple math. If you ignore that the chip may be bottlenecked for other reasons adding execution ports has diminishing returns. 1 -> 2 = 100% 2 -> 3 = 50% 3 -> 4 = 33% 4 ->...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Seems kind of pointless. The 5950X is already available for what the 5900XT is purported to retail for. The 5800X is quite a bit cheaper than what the article says the 5800XT will retail for and the extra 100 MHz isn't worth it and for most people a 5700X3D/5600X3D is probably better than either...
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    Discussion Apple Silicon SoC thread

    How well did that work out for Intel? If the competition is that far back, see if you can lap them.
  15. M

    Discussion Apple Silicon SoC thread

    Considering that Apple released M4 only 8 months after M3 and it's more than just a port over to a different node, I think any statements about their chip design team being incapable are vastly over-exaggerated.